910GL datasheet(92/426 Pages) INTEL

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.29

ERRSTS—Error Status (D0:F0)

PCI Device:

Address Offset:

C8h

Default Value:

0000h

Access:

R/WC/S, RO

Size:

16 bits

This register is used to report various error conditions via the SERR DMI messaging mechanism.

A SERR DMI message is generated on a zero to one transition of any of these flags (if enabled by

the ERRCMD and PCICMD registers). These bits are set regardless of whether or not the SERR

is enabled and generated. After the error processing is complete, the error logging mechanism can

be unlocked by clearing the appropriate status bit by software writing a 1 to it.

0Bit

Access &

Default

Description

15:13

Reserved

R/WC/S

(G)MCH Software Generated Event for SMI:

1 = This bit indicates the source of the SMI was a Device 2 Software Event.

R/WC/S

(G)MCH Thermal Sensor Event for SMI/SCI/SERR: This bit indicates that a

(G)MCH Thermal Sensor trip has occurred and an SMI, SCI, or SERR has been

generated. The status bit is set only if a message is sent based on Thermal

event enables in Error command, SMI command, and SCI command registers. A

trip point can generate one of SMI, SCI, or SERR interrupts (two or more per

event is illegal). Multiple trip points can generate the same interrupt, if software

chooses this mode, subsequent trips may be lost. If this bit is already set, an

interrupt message will not be sent on a new thermal sensor event.

Reserved

R/WC/S

LOCK to non-DRAM Memory Flag (LCKF):

1 = (G)MCH detected a lock operation to memory space that did not map into

DRAM.

R/WC/S

Received Refresh Timeout Flag(RRTOF):

1 = 1024 memory core refreshes are enqueued.

7:0

Reserved

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