910GL datasheet(78/426 Pages) INTEL

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.16

GGC—GMCH Graphics Control Register (D0:F0)

(82915G/82915GV/82915GL/82910GL GMCH only)

PCI Device:

Address Offset:

52h

Default Value:

0030h

Access:

R/W/L

Size:

16 bits

Bit

Access &

Default

Descriptions

15:7

Reserved

6:4

R/W/L

011b

Graphics Mode Select (GMS): This field is used to select the amount of main

memory that is pre-allocated to support the Internal Graphics device in VGA

(non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-

allocated only when Internal graphics is enabled. Device 2 (IGD) does not claim

VGA cycles (memory and I/O), and the Sub-Class Code field within Device 2,

Function 0 Class Code register is 80h.

000 = No memory pre-allocated

001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame buffer.

010 = Reserved.

011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame buffer.

100–111 = Reserved.

NOTES:

1. This register is locked and becomes Read Only when the D_LCK bit in the

SMRAM register is set.

2. If IGD is disabled, this field should be set to 000.

3:2

Reserved

R/W

IGD VGA Disable (IVD):

0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the Sub-Class

Code within Device 2 Class Code register is 00h.

1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and

the Sub-Class Code field within Device 2, Function 0 Class Code register is

80h.

Reserved

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