910GL datasheet(46/426 Pages) INTEL

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Signal Description

Datasheet

2.11

Reset States and Pull-up/Pull-downs

This section describes the expected states of the (G)MCH I/O buffers during and immediately

after the assertion of RSTIN#. This table only refers to the contributions on the interface from the

(G)MCH and does not reflect any external influence (such as external pull-up/pull-down resistors

or external drivers).

Legend:

CMCT:

Common Mode Center Tapped. Differential signals are weakly driven to the common

mode central voltage.

DRIVE:

Strong drive (to normal value supplied by core logic if not otherwise stated)

TERM:

Normal termination devices are turned on

LV:

Low voltage

HV:

High voltage

IN:

Input buffer enabled

ISO:

Isolate input buffer so that it doesn’t oscillate if input left floating

TRI:

Tri-state

PU:

Weak internal pull-up

PD:

Weak internal pull-down

STRAP:

Strap input sampled during assertion or on the de-asserting edge of RSTIN#

Table 2-1. Host Interface Reset and S3 States

Interface

Signal Name

I/O

State During

RSTIN#

Assertion

State After

RSTIN# De-

assertion

Pull-up/

Pull-down

Host I/F

HCPURST#

DRIVE LV

TERM HV after

approximately 1ms

TRI (No VTT)

HADSTB[1:0]#

I/O

TERM HV

TRI (No VTT)

HA[31:3]#

I/O

TERM HV

TRI (No VTT)

HD[63:0]

I/O

TERM HV

TRI (No VTT)

HDSTBP[3:0]#

I/O

TERM HV

TRI (No VTT)

HDSTBN[3:0]#

I/O

TERM HV

TRI (No VTT)

HDINV[3:0]#

I/O

TERM HV

TRI (No VTT)

HADS#

I/O

TERM HV

TRI (No VTT)

HBNR#

I/O

TERM HV

TRI (No VTT)

HBPRI#

TERM HV

TRI (No VTT)

HDBSY#

I/O

TERM HV

TRI (No VTT)

HDEFER#

TERM HV

TRI (No VTT)

HDRDY#

I/O

TERM HV

TRI (No VTT)

HEDRDY#

TERM HV

TRI (No VTT)

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