910GL datasheet(145/426 Pages) INTEL

145 / 426 page

Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

Datasheet

145

8.1.24

PM_CS1—Power Management Control/Status (D1:F0)

PCI Device:

Address Offset:

84h

Default Value:

00000000h

Access:

RO, R/W/S

Size:

32 bits

Bit

Access &

Default

Description

31:16

Reserved

PME Status: This bit indicates that this device does not support PME#

generation from D3cold.

14:13

00b

Data Scale: This field indicates that this device does not support the power

management data register.

12:9

Data Select: This field indicates that this device does not support the power

management data register.

R/W/S

PME Enable: This bit indicates that this device does not generate PMEB

assertion from any D-state.

0 = PMEB generation not possible from any D State

1 = PMEB generation enabled from any D State

The setting of this bit has no effect on hardware.

See PM_CAP[15:11]

7:2

Reserved

1:0

R/W

00b

Power State: This field indicates the current power state of this device and can

be used to set the device into a new power state. If software attempts to write an

unsupported state to this field, write operation must complete normally on the

bus, but the data is discarded and no state change occurs.

00 = D0

01 = D1 (Not supported in this device.)

10 = D2 (Not supported in this device.)

11 = D3

Support of D3cold does not require any special action.

While in the D3hot state, this device can only act as the target of PCI

configuration transactions (for power management control). This device also

cannot generate interrupts or respond to MMR cycles in the D3 state. The device

must return to the D0 state to be fully functional.

There is no hardware functionality required to support these power states.

910GL 데이터시트(PDF) 145 Page - Intel Corporation

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