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910GL 데이터시트(PDF) 216 Page - Intel Corporation

부품명 910GL
상세설명  Express Chipset
PDF  426 Pages
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제조업체  INTEL [Intel Corporation]
홈페이지  http://www.intel.com
Logo INTEL - Intel Corporation

910GL 데이터시트(HTML) 216 Page - Intel Corporation

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System Address Map
R
216
Datasheet
11.3.8
Graphics Memory Address Ranges (Intel
®
82915G/82915GV/82915GL/82910GL GMCH Only)
The GMCH can be programmed to direct memory accesses to IGD when addresses are within any
of three programmable ranges.
• The Memory Map Base Register (MMADR) is used to access graphics control registers.
• The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory
allocated via the graphics translation table.
• The Graphics Translation Table Base Register (GTTADR) is used to access the translation
table.
Normally these ranges will reside above the Top-of-Main-DRAM and below High BIOS and
APIC address ranges. They normally reside above the top of memory (TOLUD) so that physical
DRAM memory space is not allocate to them.
The memory allocated via the graphics translation table is a Prefetchable range to apply USWC
attribute (from the processor point of view) to that range. The USWC attribute is used by the
processor for write combining.
11.4
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM RAM). The
(G)MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of
Memory Segment (TSEG). System Management RAM space provides a memory area that is
available for the SMI handlers and code and data storage. This memory resource is normally
hidden from the system OS so that the processor has immediate access to this memory space upon
entry to SMM. (G)MCH provides three SMRAM options:
• Below 1-MB option that supports compatible SMI handlers.
• Above 1-MB option that allows new SMI handlers to execute with write-back cacheable
SMRAM.
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. For the
82915G/82915GV/82915GL/82910GL GMCH, the TSEG area lies below IGD stolen
memory.
The above 1-MB solutions require changes to compatible SMRAM handler’s code to properly
execute above 1 MB.
Note:
DMI and PCI Express masters are not allowed to access the SMM space.



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