C5NPD0-DS datasheet(41/100 Pages) FREESCALE

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Pin Descriptions Grouped by Function

V 04

of the devices connected to the bus must have either an open-drain or open-collector in

order to perform the wired-AND function required for its arbitration mechanism.

PROM Interface Signals

The PROM interface is a low speed I/O port that allows the C-5 NP to communicate

through external logic to PROM. The PROM clock is 1/

2 to

16 the core clock rate. The

maximum PROM size is 4MBytes x 16, and configuration is required. The PROM signals are

listed in Table 16.

Figure 4 shows the connections between the PROM Interface and external board logic.

The application is required to provide an external shift register with parallel-in and

parallel-out capabilities, and a parallel load register. Both devices should be

Table 15 Serial Port Signals

SIGNAL NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

SICL

O14

LVTTL

I/O

Serial Clock line

SIDA

N14

LVTTL

I/O

Serial Data line

TOTAL PINS

Table 16 PROM Interface Signals

SIGNAL

NAME

PIN #

TOTAL

TYPE

I/O

SIGNAL DESCRIPTION

SPDO

N15

LVTTL

Serial Data Out

SPDI

N16

LVTTL

Serial Data In

SPLD

M16

LVTTL

When load is asserted on a positive clock

edge, the external logic performs a parallel

load. On each positive clock edge when

load is de-asserted, the shift registers shift.

When the PROM interface is idle:

• if SPLD is asserted HI it indicates low

speed serial protocol,

• if asserted LOW it indicates MDIO serial

protocol.

SPCK

M14

LVTTL

Clock

TOTAL PINS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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