C5NPD0-DS datasheet(42/100 Pages) FREESCALE

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CHAPTER 2: SIGNAL DESCRIPTIONS

C5NP

positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When

SPLD is deasserted the shift register shifts.

Figure 4 PROM Interface Diagram

The PROM interface operates in the following manner:

Two accesses are piplined together to execute one 32-bit fetch. The steps are shown in

Figure 5

1 The PROM_ADDR is loaded into the network processor internal shift register.

2 The PROM_ADDR is shifted into the external shift register for 22 SPCLK cycles.

3 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external

presentation register.

4 SPLD is deasserted for 22 SPCLK cycles. The PROM presents the first 16bit

PROM_DATA. At the same time, the next PROM_ADDR is shifted into the external shift

5 SPLD is asserted for one SPCLK cycle, loading the PROM_ADDR into the external

presentation register and the first PROM_DATA into the external shift register.

6 SPLD is deasserted for 22 SPCLK cycles, shifting the first PROM_DATA into the network

processor internal shift register.

External Logic

PROM_ADDR<21:1>

PROM _H_Word

C-5 Network Processor

PROM Clock Gen.

PROM _Return_Data

PROM Sequencer

SPCLK

SPLD

SPDO

SPDI

Internal Shift

PROM_ADDR<21:1>

PROM _LO_Word

PROM

PROM_Data

External Shift Register

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