ADSP-21469KBZ-ENG2 datasheet(26/56 Pages) AD

26 / 56 page

Rev. PrB

Page 26 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Table 22. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

tPCGIW

Input Clock Period

TBD

tSTRIG

PCG Trigger Setup Before Falling Edge of PCG Input

Clock

TBD

tHTRIG

PCG Trigger Hold After Falling Edge of PCG Input

Clock

TBD

Switching Characteristics

tDPCGIO

PCG Output Clock and Frame Sync Active Edge Delay

After PCG Input Clock

TBD

tDTRIGCLK

PCG Output Clock Delay After PCG Trigger

TBD

tDTRIGFS

PCG Frame Sync Delay After PCG Trigger

TBD

tPCGOW

Output Clock Period

TBD

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2146x SHARC Processor Hardware Reference, “Precision Clock Generators”

chapter.

1 Normal mode of operation.

Figure 14. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

DPI_Pn

PCG_TRIGx_I

tSTRIG

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

DPI_Py

PCG_CLKx_O

DAI_Pz

DPI_Pz

PCG_FSx_O

tHTRIG

tDPCGIO

tDTRIGFS

tPCGIW

tPCGOW

tDTRIGCLK

tDPCGIO

ADSP-21469KBZ-ENG2 데이터시트(PDF) 26 Page - Analog Devices

ADSP-21469KBZ-ENG2 데이터시트(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

데이터시트 다운로드

링크 URL