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ADSP-21469KBZ-ENG2 데이터시트(PDF) 33 Page - Analog Devices

부품명 ADSP-21469KBZ-ENG2
상세설명  SHARC Processor material that is subject to change without notice
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ADSP-21469/ADSP-21469W
Preliminary Technical Data
Rev. PrB
|
Page 33 of 56
|
November 2008
Table 29. Link Ports – Transmit
Parameter
Min
Max
Unit
Timing Requirements
tSLACH
LACK Setup Before LCLK High
TBD
TBD
ns
tHLACH
LACK Hold After LCLK High
TBD
TBD
ns
Switching Characteristics
TBD
TBD
tDLDCH
Data Delay After LCLK High
TBD
TBD
ns
tHLDCH
Data Hold After LCLK High
TBD
TBD
ns
tLCLKTWL
LCLK Width Low
TBD
TBD
ns
tLCLKTWH
LCLK Width High
TBD
TBD
ns
tDLACLK
LCLK Low Delay After LACK High
TBD
TBD
ns
Figure 21. Link Ports—Transmit
LCLK
LDAT7-0
LACK (IN)
THE
tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST BYTE TRANSMITTED.
LASTBYTE
TRANSMITTED
FIRSTBYTE
TRANSMITTED
LCLK INACTIVE
(HIGH)
OUT
tDLDCH
tHLDCH
tLCLKTWH
tLCLKTWL
tSLACH
tHLACH
tDLACLK



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