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ADSP-21469KBZ-ENG2 데이터시트(PDF) 46 Page - Analog Devices

부품명 ADSP-21469KBZ-ENG2
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ADSP-21469KBZ-ENG2 데이터시트(HTML) 46 Page - Analog Devices

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Rev. PrB
|
Page 46 of 56
|
November 2008
ADSP-21469/ADSP-21469W
Preliminary Technical Data
SPI Interface—Slave
Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Min
Max
Unit
Timing Requirements
tSPICLKS
Serial Clock Cycle
TBD
TBD
ns
tSPICHS
Serial Clock High Period
TBD
TBD
ns
tSPICLS
Serial Clock Low Period
TBD
TBD
ns
tSDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
TBD
TBD
TBD
TBD
ns
ns
tHDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
TBD
TBD
ns
tSSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time)
TBD
TBD
ns
tHSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
TBD
TBD
ns
tSDPPW
SPIDS Deassertion Pulse Width (CPHASE=0)
TBD
TBD
ns
Switching Characteristics
tDSOE
SPIDS Assertion to Data Out Active
TBD
TBD
ns
tDSDHI
SPIDS Deassertion to Data High Impedance
TBD
TBD
ns
tDDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
TBD
TBD
ns
tHDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
TBD
TBD
ns
tDSOV
SPIDS Assertion to Data Out Valid (CPHAS E = 0)
TBD
TBD
ns
Figure 35. SPI Slave Timing
tHSPIDS
tDDSPIDS
tDSDHI
LSB
MSB
MSBVALID
tDSOE
tDDSPIDS
tHDSPIDS
MISO
(OUTPUT)
MOSI
(INPUT)
tSSPIDS
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(CP = 1)
(INPUT)
tSDSCO
tSPIC HS
tSPICLS
tSPICLS
tSPICLKS
tHDS
tSPICHS
tSSPIDS
tHSPIDS
tDSDHI
LSBVALID
MSB
MSBVALID
tDDSPIDS
MISO
(OUTPUT)
MOSI
(INPUT)
tSSPIDS
LSBVALID
LSB
CPHASE= 1
CPHASE= 0
tSDPPW
tDSOV
tHDSPIDS



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