전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

ADSP-21469KBZ-ENG2 데이터시트(PDF) 45 Page - Analog Devices

부품명 ADSP-21469KBZ-ENG2
상세설명  SHARC Processor material that is subject to change without notice
PDF  56 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADSP-21469KBZ-ENG2 데이터시트(HTML) 45 Page - Analog Devices

Back Button ADSP-21469KBZ-ENG2 Datasheet HTML 41Page - Analog Devices ADSP-21469KBZ-ENG2 Datasheet HTML 42Page - Analog Devices ADSP-21469KBZ-ENG2 Datasheet HTML 43Page - Analog Devices ADSP-21469KBZ-ENG2 Datasheet HTML 44Page - Analog Devices ADSP-21469KBZ-ENG2 Datasheet HTML 45Page - Analog Devices ADSP-21469KBZ-ENG2 Datasheet HTML 46Page - Analog Devices ADSP-21469KBZ-ENG2 Datasheet HTML 47Page - Analog Devices ADSP-21469KBZ-ENG2 Datasheet HTML 48Page - Analog Devices ADSP-21469KBZ-ENG2 Datasheet HTML 49Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 45 / 56 page
background image
ADSP-21469/ADSP-21469W
Preliminary Technical Data
Rev. PrB
|
Page 45 of 56
|
November 2008
SPI Interface—Master
The ADSP-21469 contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 42 and Table 43 applies to both.
Table 42. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
Data Input Valid To SPICLK Edge (Data Input Setup Time)
TBD
TBD
ns
tHSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid
TBD
TBD
ns
Switching Characteristics
tSPICLKM
Serial Clock Cycle
TBD
TBD
ns
tSPICHM
Serial Clock High Period
TBD
TBD
ns
tSPICLM
Serial Clock Low Period
TBD
TBD
ns
tDDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
TBD
TBD
tHDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
TBD
TBD
ns
tSDSCIM
FLAG3–0IN (SPI device select) Low to First SPICLK Edge
TBD
TBD
ns
tHDSM
Last SPICLK Edge to FLAG3–0IN High
TBD
TBD
ns
tSPITDM
Sequential Transfer Delay
TBD
TBD
ns
Figure 34. SPI Master Timing
LSB
VALID
MSB
VALID
tSSPIDM
tHSPIDM
tHDSPIDM
LSB
MSB
tHSPIDM
tDDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
FLAG3
-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
tSPICHM
tSPICLM
tSPICLM
tSPICLKM
tSPICHM
tHDSM
tSPITDM
tHDSPIDM
LSB
VALID
LSB
MSB
MSB
VALID
tHSPIDM
tDDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
tSSPIDM
CPHASE= 1
CPHASE= 0
tSDSCIM
tSSPIDM



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com