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ADSP-21469KBZ-ENG2 데이터시트(PDF) 36 Page - Analog Devices |
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ADSP-21469KBZ-ENG2 데이터시트(HTML) 36 Page - Analog Devices |
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36 / 56 page ![]() Rev. PrB | Page 36 of 56 | November 2008 ADSP-21469/ADSP-21469W Preliminary Technical Data Figure 23. Serial Ports DRIVE EDGE DAI_P20 -1 SCLK (INT) DRIVE EDGE DRIVE EDGE SCLK DAI_P20 -1 SCLK (EXT) tDDTTE tDDTEN tDDTIN DAI_P20 -1 (DATA CHANNEL A/B) DAI_P20-1 (DATA CHANNEL A/B) DAI_P20 -1 (SCLK) DAI_P20 -1 (FS) DRIVE EDGE SAMPLE EDGE DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. tSDRI tHDRI tSFSI tHFSI tDFSIR tHOFSIR tSCLKIW tSDRE tHDRE tSFSE tHFSE tDFSE tSCLKW tHOFSE DAI_P20 -1 (DATA CHANNEL A/B) tDDTI DRIVE EDGE SAMPLE EDGE DATA TRANSMIT—INTERNAL CLOCK tSFSI tHFSI tDFSI tHOFSI tSCLKIW tHDTI NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. tDDTE DRIVE EDGE SAMPLE EDGE DATA TRANSMIT—EXTERNAL CLOCK tSFSE tHFSE tDFSE tHOFSE tSCLKW tHDTE DAI_P20 -1 (SCLK) DAI_P20 -1 (FS) DAI_P20 -1 (DATA CHANNEL A/B) DAI_P20 -1 (SCLK) DAI_P20 -1 (FS) DAI_P20 -1 (DATA CHANNEL A/B) DAI_P20 -1 (SCLK) DAI_P20 -1 (FS) DAI_P20 -1 (DATA CHANNEL A/B) |
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