ADSP-21469KBZ-ENG2 datasheet(24/56 Pages) AD

24 / 56 page

Rev. PrB

Page 24 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts as well as the DAI_P20-1 and

DPI_P14-1 pins when they are configured as interrupts.

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0 and

Timer1 in PWM_OUT (pulse-width modulation) mode. Timer

signals are routed to the DPI_P14–1 pins through the DPI SRU.

Therefore, the timing specifications provided below are valid at

the DPI_P14–1 pins.

Table 17. Interrupts

Parameter

Min

Max

Unit

Timing Requirement

tIPW

IRQx Pulse Width

TBD

Figure 9. Interrupts

DAI_P20-1

DPI_P14-1

FLAG2-0

(IRQ2-0)

tIPW

Table 18. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

tWCTIM

CTIMER Pulse Width

TBD

Figure 10. Core Timer

FLAG3

(CTIMER)

tWCTIM

Table 19. Timer PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

tPWMO

Timer Pulse Width Output

TBD

Figure 11. Timer PWM_OUT Timing

DPI_P14-1

(TIMER1-0)

tPWMO

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