LE25LB642CT

AC Characteristics (at FCLK = 3MHz)/VDD = 1.8V to 3.6V

Parameter

Symbol

Conditions

min

typ

max

Unit

Clock frequency

FCLK

3

MHz

SCK logic high level pulse width

tCLHI

120

ns

SCK logic low level pulse width

tCLLO

120

ns

Input signal rise/fall time

tRF

1

us

CS setup time

tCSS

100

ns

SCK setup time

tCLS

100

ns

Data setup time

tDS

30

ns

Data hold time

tDH

50

ns

No.NA1471-4/14

CS hold time

tCSH

100

ns

SCK hold time

tCLH

150

ns

CS standby pulse width

tCPH

120

ns

CS output high impedance time

tCHZ

200

ns

SCK output data time

tV

150

ns

Output data hold time

tHO

0

ns

WP setup time

tWPS

30

ns

WP hold time

tWPH

30

ns

HOLD setup time

tHS

30

ns

HOLD hold time

tHH

30

ns

HOLD output low impedance time

tHLz

120

ns

HOLD output high impedance time

tHHz

120

ns

Write cycle time

tWC

10

ms

SCK output low impedance time

tCLZ

0

ns

Table 1 Command Settings

Command

1st bus

cycle

2nd bus

cycle

3rd bus

cycle

4th bus

cycle

5th bus

cycle

6th bus

cycle

nth bus

cycle

Write enable

(WREN)

06h

Write disable

(WRDI)

04h

Status register read

(RDSR)

05h

Status register write

(WRSR)

01h

DATA

Read

(READ)

03h

A15-A8

A7-A0

Write

(WRITE)

02h

A15-A8

A7-A0

PD *1

PD *1

PD *1

PD *1

Explanatory notes for Table 1

The “h” following each code indicates that the number given is in hexadecimal notation.

Addresses A15 - A13 for all commands are “don’t care.”

*1: “PD” stands for page program data. Any amount of data from 1 to 32 bytes is input.