MMA8652FC datasheet(33/77 Pages) FREESCALE

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MMA8652FC

Sensors

Freescale Semiconductor, Inc.

6.6.2

0x0C: INT_SOURCE System Interrupt Status register

In the interrupt source register, the status of the various embedded features can be determined.

•

The bits that are set (logic ‘1’) indicate which function has asserted an interrupt.

•

The bits that are cleared (logic ‘0’) indicate which function has not asserted (or has deasserted) an interrupt.

INT_SOURCE register bits are set by a low-to-high transition, and are cleared by reading the appropriate interrupt source register.

For example, the SRC_DRDY bit is cleared when the ZYXDR bit (STATUS register) is cleared, but the SRC_DRDY bit is not

cleared by simply reading the STATUS register (0x00), but is cleared by reading all the X, Y, and Z MSB data.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SRC_ASLP

SRC_FIFO

SRC_TRANS

SRC_LNDPRT

SRC_PULSE

SRC_FF_MT

—

SRC_DRDY

Figure 26. 0x0C INT_SOURCE: System Interrupt Status register (Read Only)

Table 20. INT_SOURCE register

Bit(s)

Field

Description

SRC_ASLP

Auto-SLEEP/WAKE interrupt status bit

• WAKE-to-SLEEP transition occurs when no interrupt occurs for a time period that exceeds the user-

specified limit (ASLP_COUNT). This causes the system to transition to a user-specified low ODR setting.

• SLEEP-to-WAKE transition occurs when the user-specified interrupt event has woken the system; thus

causing the system to transition to a user-specified high ODR setting.

• Reading the SYSMOD register clears the SRC_ASLP bit.

1 An interrupt event that can cause a WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition has

occurred.

0 No WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition interrupt event has occurred. (default)

6SRC_FIFO

FIFO interrupt status bit

• FIFO interrupt event generators: FIFO Overflow, or (Watermark: F_CNT = F_WMRK) and the interrupt has

been enabled.

• SRC_FIFO bit is cleared by reading the F_STATUS register.

1 A FIFO interrupt event (such as an overflow event or watermark) has occurred.

0 No FIFO interrupt event has occurred. (default)

SRC_TRANS

Transient interrupt status bit

• SRC_TRANS bit is asserted whenever the EA bit (TRANS_SRC register) is asserted and the interrupt has

been enabled.

• SRC_TRANS bit is cleared by reading the TRANS_SRC register.

1An acceleration transient value greater than user-specified threshold has occurred.

0 No transient event has occurred. (default)

SRC_LNDPRT

Landscape/Portrait Orientation interrupt status bit

• SRC_LNDPRT bit is asserted whenever the NEWLP bit (PL_STATUS register) is asserted and the interrupt

has been enabled.

• SRC_LNDPRT bit is cleared by reading the PL_STATUS register.

1 An interrupt was generated due to a change in the device orientation status.

0 No change in orientation status was detected. (default)

SRC_PULSE

Pulse interrupt status bit

• SRC_PULSE bit is asserted whenever the EA bit (PULSE_SRC register) is asserted and the interrupt has

been enabled.

• SRC_PULSE bit is cleared by reading the PULSE_SRC register.

1 An interrupt was generated due to single and/or double pulse event.

0 No pulse event was detected. (default)

SRC_FF_MT

Freefall/Motion interrupt status bit

• SRC_FF_MT bit is asserted whenever the EA bit (FF_MT_SRC register) is asserted and the FF_MT

interrupt has been enabled.

• SRC_FF_MT bit is cleared by reading the FF_MT_SRC register.

1 The Freefall/Motion function interrupt is active.

0 No Freefall or Motion event was detected. (default)

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