MMA8652FC datasheet(18/77 Pages) FREESCALE

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MMA8652FC

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Freescale Semiconductor, Inc.

•The I2C interface may be used for communications between other I2C devices; the MMA8652FC does not affect the I2C

bus.

The I2C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards (Table 6).

I2C operation:

The transaction on the bus is started through a start condition (START) signal. A START condition is defined as a high-to-

low transition on the data line while the SCL line is held high. After START has been transmitted by the Master, the bus is

considered busy.

The next byte of data transmitted after START contains the slave address in the first 7 bits, and the 8th bit tells whether

the Master is receiving data from the slave or is transmitting data to the slave.

After a start condition and when an address is sent, each device in the system compares the first 7 bits with its address.

If the device’s address matches the sent address, then the device considers itself addressed by the Master.

The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The

transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low, so that it

remains stable low during the high period of the acknowledge clock period.

A Master may also issue a repeated START during a data transfer. The MMA8652FC expects repeated STARTs to be

used to randomly read from specific registers.

A low-to-high transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer

is always terminated by a STOP.

The MMA8652FC's standard slave address is 0011101 or 0x01D. The slave addresses are factory programmed; alternate

addresses are available upon request.

5.11.1

Single byte read

The transmission of an 8-bit command begins on the falling edge of SCL. After the 8 clock cycles are used to send the

command, note that the data returned is sent with the MSB first after the data is received. Figure 11 shows the timing

diagram for the accelerometer 8-bit I2C read operation.

The Master (or MCU) transmits a start condition (ST) to the MMA8652FC [slave address (0x1D), with the R/W bit set to

“0” for a write], and the MMA8652FC sends an acknowledgement.

Next the Master (or MCU) transmits the address of the register to read, and the MMA8652FC sends an

acknowledgement.

The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA8652FC (0x1D), with the R/

W bit set to “1” for a read from the previously selected register.

The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge

(NAK) the transmitted data, but transmits a stop condition to end the data transfer.

Figure 11. Single Byte Read timing (I2C)

Table 10. Serial Interface pins

Pin Name

Pin Description

Notes

SCL

I2C Serial Clock

There are two signals associated with the I2C bus; the Serial Clock Line (SCL) and the

Serial Data line (SDA).

• SDA is a bidirectional line used for sending and receiving the data to/from the interface.

• External pullup resistors connected to VDDIO are expected for SDA and SCL. When the bus

is free, both SCL and SDA lines are high.

SDA

I2C Serial Data

Table 11. I2C Device address sequence

Command

[6:0]

Device address

[6:0]

Device address

R/W

8-bit final

value

Read

0011101

0x1D

0x3B

Write

0011101

0x1D

0x3A

Master

ST Device Address[7:1]

Address[7:0]

SR Device Address[7:1]

NAK

Slave

Data[7:0]

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