MMA8652FC datasheet(59/77 Pages) FREESCALE

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MMA8652FC

Sensors

Freescale Semiconductor, Inc.

6.12

Auto-WAKE/SLEEP register

6.12.1

0x29: ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write)

The ASLP_COUNT register sets the minimum time period of inactivity required to switch the part between Wake and Sleep

status. At the end of the time period, the device switches its ODR rate automatically when the Auto-WAKE /SLEEP function is

enabled.

•

Wake ODR is set by CTRL_REG1[DR] bits.

•

Sleep ODR is set by CTRL_REG1[ASLP_RATE] bits.

•

Auto WAKE/SLEEP function is enabled by asserting the CTRL_REG2[SLPE] bit.

D7–D0 defines the minimum duration time needed to change the current ODR value from DR to ASLP_RATE. The time step and

maximum value depend on the ODR chosen (as shown in Table 60).

For functional blocks that may be monitored for inactivity (to trigger the “return to SLEEP” event), see Table 61.

•

4 interrupt sources can WAKE the device: Transient, Orientation, Tap, and the Motion/Freefall. One or more of these

functions can be enabled.

—

To WAKE the device, the desired function(s) must be enabled in CTRL_REG4 register and set to WAKE-to-SLEEP

in CTRL_REG3 register.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Figure 53. 0x29 ASLP_COUNT register (Read/Write)

Table 59. ASLP_COUNT register

Bit(s)

Field

Description

7–0

D[7:0]

Duration value

0000_0000 (default)

Table 60. ASLP_COUNT relationship with ODR

Output Data Rate

(ODR)

Duration

(sec)

ODR Time Step

(ms)

ASLP_COUNT Step

(ms)

800 Hz

0 to 81

1.25

320

400 Hz

0 to 81

2.5

320

200 Hz

0 to 81

320

100 Hz

0 to 81

320

50 Hz

0 to 81

320

12.5 Hz

0 to 81

320

6.25 Hz

0 to 81

160

320

1.56 Hz

0 to 162

640

Table 61. SLEEP/WAKE mode gates and triggers

Interrupt Source

Will the event restart the timer

and delay “Return to SLEEP”?

Will the event

WAKE from SLEEP?

Notes

FIFO_GATE

Yes

* If the FIFO_GATE bit is set to 1, then the assertion of the

SRC_ASLP interrupt does not prevent the system from

transitioning to SLEEP or from WAKE mode; instead the

assertion of the interrupt prevents the FIFO buffer from

accepting new sample data—until the host application

flushes the FIFO buffer.

SRC_TRANS

Yes

SRC_LNDPRT

Yes

SRC_PULSE

Yes

SRC_FF_MT

Yes

SRC_ASLP

No*

SRC_DRDY

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