MMA8652FC datasheet(67/77 Pages) FREESCALE

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MMA8652FC

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Freescale Semiconductor, Inc.

6.13.5

0x2E CTRL_REG5 Interrupt Configuration register (Read/Write)

CTRL_REG5 register maps the desired interrupts to INT2 or INT1 pins.

The system’s interrupt controller (shown in Figure 10) uses the corresponding bit field in the CTRL_REG5 register, to determine

the routing table for the INT1 and INT2 interrupt pins.

•

If the bit value is 0, then the functional block’s interrupt is routed to INT2.

•

If the bit value is 1, then the functional block’s interrupt is routed to INT1.

One or more functions can assert an interrupt pin; therefore a host application responding to an interrupt should read the

INT_SOURCE (0x0C) register, to determine the appropriate sources of the interrupt.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT_CFG_ASLP

INT_CFG_FIFO

INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE

INT_CFG_FF_MT

INT_CFG_DRDY

Figure 58. 0x2E: CTRL_REG5 Interrupt Configuration register

Table 71. 0x2E CTRL_REG5 register

Bit(s)

Field

Description

INT_CFG_ASLP

Auto-SLEEP/WAKE INT1/INT2 Configuration

0 Interrupt is routed to INT2 pin (default)

1 Interrupt is routed to INT1 pin

6INT_CFG_FIFO

FIFO INT1/INT2 Configuration

5INT_CFG_TRANS

Transient INT1/INT2 Configuration

INT_CFG_LNDPRT

Orientation INT1/INT2 Configuration

3INT_CFG_PULSE

Pulse INT1/INT2 Configuration

2INT_CFG_FF_MT

Freefall/motion INT1/INT2 Configuration

INT_CFG_DRDY

Data Ready INT1/INT2 Configuration

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