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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA321 데이터시트(PDF) 23 Page - STMicroelectronics |
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STA321 데이터시트(HTML) 23 Page - STMicroelectronics |
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23 / 157 page  STA321 Power-up and power-down sequences Doc ID 15351 Rev 3 23/157 4.3 Hardware power-down mode The hardware power-down is obtained by asserting pin STBY to high. There are two power-down options available, namely mild mode and full (or deep) mode, that could be selected using the DC_STBY_EN signal in register STBY_MODES Figure 8 summarizes the main power-down sequence. “Power on” is the normal operating status where all the startup procedures have already been executed. The rectangular boxes indicate the steps to be done by the user whilst the rounded boxes indicate the steps done by the device. Figure 8. Hardware power-done sequence Power-down mode YES NO CMP_EN_N = 1 ? Comp Cell Pwdn NO DC_STBY_EN = 1 ? YES DC Reg. Stby Embedded amp. CMOS bridge Powerdown Power on Pin STBY <= 1' CLK_I2C off CLK Core off CLK_ADC off PLL power down I 2C programming register STBY_MODES bits: CMP_EN_N DC_STBY_EN |
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