STA321 datasheet(25/157 Pages) STMICROELECTRONICS

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STA321

Power-up and power-down sequences

Doc ID 15351 Rev 3

25/157

4.3.1

Mild power-down

In this case, the device is put into a mild power-down mode.

All the peripherals are set to standby and their clocks turned off.

The I2C configuration is not required as the default values of the registers are sufficient.

Initial conditions:

FFX_ULCK_PLL = 10

CMP_EN_N = 0

DC_STBY_EN = 0

Going into power-down:

After the assertion of the pin STBY, the following actions are taken by the device:

Embedded amplifier (EA) and CMOS bridge (CB) volume are set to mute (the length of

this step changes according to the fade-out ramp configuration).

EA and CB are put into power-down.

After the previous operation is completed:

All peripherals are turned off (regardless the register settings).

The PLL clock is bypassed, the system clock (sys_clk in Figure 11 on page 29) is XTI.

All clocks are shut down.

Returning to normal mode:

After the release of the pin STBY, the power-up procedure takes place:

All clocks are turned on.

All peripherals are restored to their previous status (based on the last register settings).

If the PLL clock was the system clock it will be selected again after the locking time.

The EA and the CB execute the fade-in procedure before becoming ready to be used

(the length of this step changes according to the fade-in ramp configuration).

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