STW82102B datasheet(23/67 Pages) STMICROELECTRONICS

23 / 67 page

STW82102B

General description

Doc ID 018516 Rev 2

23/67

General description

The STW82102B (see Figure 1: STW82102B block diagram on page 7) consists of a high

linearity passive CMOS mixer with integrated RF balun, an IF amplifier, a 10-bit current

steering DAC with dual output, and an integrated integer-N synthesizer.

The synthesizer embeds 2 internal low-noise VCOs with buffer blocks, a divider by 2, a low

noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit programmable

reference divider, two programmable counters and a dual-modulus prescaler. The A-counter

(5 bits) and B counter (12 bits) counters, in conjunction with the dual modulus prescaler

P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P+A.

The device is controlled through a digital interface (I2C bus interface or SPI digital interface).

All internal devices operate with a power supply of 3.3 V except for the IF Amplifier output

stage and the mixer driver stage operating at 5 V power supply in order to maximize the

linearity performance. If the application requires a reduced linearity and noise figure

performance the device is programmed in a low-current mode by using the minimum LO

amplitude and the minimum biasing current in the IF amplifier. In low-current mode

operation the device can use only the 3.3 V power supply thus dissipating less power.

8.1

Circuit description

8.1.1

Reference input stage

The reference input stage is shown in Figure 9. The resistor network feeds a DC bias at the

Fref input while the inverter used as the frequency reference buffer is AC coupled.

Figure 9.

Reference frequency input buffer

Fref

VDD

Inverter

Power Down

Buffer

STW82102B 데이터시트(PDF) 23 Page - STMicroelectronics