OR3LP26B datasheet(85/184 Pages) AGERE

85 / 184 page

Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Table 30. Quad-Port FIFO Packing/Unpacking, Case 1, PCI Side

Table 31. Quad-Port FIFO Packing/Unpacking, Case 1, FPGA Side

Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.

Dummy words are unknown data words in the FIFOs with their byte enables disabled.

Case 2: Target write burst, 32-bit. Quadword aligned starting address, odd number of 32-bit words transferred on

the PCI bus.

Table 32. Quad-Port FIFO Packing/Unpacking, Case 2, PCI Side

Table 33. Quad-Port FIFO Packing/Unpacking, Case 1, FPGA Side

Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.

Dummy words are unknown data words in the FIFOs with their byte enables disabled.

PCI Address

PCI Data

PCI Byte Enables

(Active-Low)

00001000

32-bit Word1

0000

(00001004)

32-bit Word2

0000

(00001008)

32-bit Word3

0000

(00001010)

32-bit Word4

0000

(00001014)

32-bit Word5

0000

(00001018)

32-bit Word6

0000

Master Write FIFO Slot

FIFO Data Bits [31:0]

FIFO Byte Enables

(Active-Low)

twdata[31:0]

twdata[35:32]

32-bit Word1

0000

32-bit Word2

0000

32-bit Word3

0000

32-bit Word4

0000

32-bit Word5

0000

32-bit Word6

0000

PCI Address

PCI Data

PCI Byte Enables

(Active-Low)

00001000

32-bit Word1

0000

(00001004)

32-bit Word2

0000

(00001008)

32-bit Word3

0000

(00001010)

32-bit Word4

0000

(00001014)

32-bit Word5

0000

Master Write FIFO Slot

FIFO Data Bits [31:0]

FIFO Byte Enables

(Active-Low)

twdata[31:0]

twdata[35:32]

32-bit Word1

0000

32-bit Word2

0000

32-bit Word3

0000

32-bit Word4

0000

32-bit Word5

0000

Dummy Word

FFFF

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