OR3LP26B datasheet(14/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description

The following sections describe the operation of the embedded core PCI bus interface.

PCI Bus Commands

The PCI core supports all commands required by the PCI specification. The following table describes each com-

mand. Subsequent sections will describe the protocols in which the commands are used.

Table 4. PCI Bus Command Descriptions

Command

Code

(Binary

)

Command

Master

Generates

Target

Accepts

Description

0000

Interrupt

Acknowl-

edge

—

Only implemented as Master by agents that interface to the sys-

tem CPU and as Target by agents that incorporate the system

interrupt controller.

0001

Special

Cycle

—

Target ignores, per PCI Specification section 3.6.2.

0010

I/O Read

√√

Fully implemented.

Target: Bursting is prevented by disconnecting with data on the

first data phase. If signal deltrn is asserted low, I/O (and memory)

reads are handled as delayed transactions; no wait-states are

generated. If signal deltrn is deasserted high, the unit waits for the

data from the FPGA application, inserting wait-states (up to the

maximum allowed, after which a retry is issued).

Master: Bursting is allowed, and no wait-states are generated.

0011

I/O Write

√√

Fully implemented.

Target: Bursting is prevented by disconnecting with data on the

first data phase. If signal deltrn is asserted low, I/O writes are

handled as delayed transactions; no wait-states are generated.

Master: Bursting is allowed, and no wait-states are generated.

0100

(reserved)

—

Target ignores, per PCI Specification section 3.1.1.

0101

(reserved)

—

Target ignores, per PCI Specification section 3.1.1.

0110

Memory

Read

√√

Fully implemented.

Target: Bursting is allowed. If signal deltrn is asserted low, mem-

ory (and I/O) reads are handled as delayed transactions. If signal

deltrn is deasserted high, the unit waits for the data from the

FPGA application, inserting wait-states (up to the maximum

allowed, after which a retry is issued). If signal trburstpendn is

asserted low and the Target Read FIFO is empty, wait-states are

inserted (up to the maximum allowed, after which a retry is

issued).

Master: Bursting is allowed, and no wait-states are generated.

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