OR3LP26B datasheet(60/184 Pages) AGERE

60 / 184 page

Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual

Port (continued)

Reset

The FPGA application can apply the PCI core’s reset

signal tfifoclrn to place the core’s target logic in a

known state. Normally, the clear signal will not be used

unless a severe problem has occurred in the data flow.

The tfifoclrn signal is synchronous with fclk and must

be asserted for a minimum of three clock periods. Dur-

ing reset, the t_ready signal will go low. After the reset

signal is deasserted high, t_ready will continue to be

low for 8—10 clock periods. The FPGA application

should not continue normal operation until t_ready is

asserted high.

Understanding and Using the pci_tcfg_stat Status

Signals

On the Target interface, there are two signals that con-

trol and provide status to the FPGA application. The

signal pci_tcfg_stat provides the status, and tcfg-

shiftenn controls what information the status line pro-

vides. The pci_tcfg_stat signal is always active and

duplicates the status contained in configuration status

use this status output, the FPGA application must keep

tcfgshiftenn = 1. When high, pci_tcfg_stat provides

the wired-OR of the three status lines. If pci_tcfg_stat

gets set to a 1, indicating an error, then the FPGA

application may set tcfgshiftenn = 0 to determine indi-

vidual status. Once low, the pci_tcfg_stat signal will

output target abort signaled on the first clock, system

error signaled on the second clock, and parity error

detected on the third clock.

Initiating Target Aborts

There may be a need in an application to initiate a tar-

get abort condition on the PCI bus. In general, this is

asserted for only the most severe cases. The interface

signal, fpga_tabort, is used for this purpose. From the

PCI core's point of view, it needs to know whether to

perform a target abort at the very beginning of a trans-

action, so it is not possible to have a transaction

started, and then assert the fpga_tabort signal. The

signal fpga_tabort needs to be asserted before the

transaction begins, and it was designed to be toggled

on and off from transaction to transaction. Once an

FPGA application determines that it wants to apply a

target abort to any master that accesses it, it would

assert the fpga_tabort signal high. All future target

accesses will be terminated in an abort. In generating

this signal, keep in mind that this signal needs to be

synchronous to pciclk.

OR3LP26B 데이터시트(PDF) 60 Page - Agere Systems

OR3LP26B 데이터시트(HTML) 60 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL