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OR3LP26B 데이터시트(PDF) 98 Page - Agere Systems

부품명 OR3LP26B
상세설명  Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
PDF  184 Pages
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OR3LP26B 데이터시트(HTML) 98 Page - Agere Systems

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ORCA OR3LP26B FPSC
Data Sheet
Embedded Master/Target PCI Interface
March 2000
98
Lucent Technologies Inc.
Lucent Technologies Inc.
PCI Bus Core Detailed Description Quad Port (continued)
Master Read, Burst Transaction
Figure 32 (FPGA bus) and Figure 31 (PCI bus) show the timing of a four Quadword Master read burst. Operation is
similar to that in the Master read, nonburst transaction, but extra data words are supplied by the FPGA application.
In Figure 32, the transaction is initiated by the FPGA application asserting Master address enable (maenn), while
providing the command and burst length on bus mwdata. On the next clock, the FPGA application provides the
DWORD address and asserts mwlastcycn. On the third cycle, both maenn and mwlastcycn are deasserted. PCI
bus activity now begins as shown in Figure 31. Once data is transferred on the PCI bus and mr_emptyn is deas-
serted high, the FPGA application asserts mrdataenn and eight DWORDs of data are transferred on bus mrdata.
5-8850(F).a
Figure 31. Master Read 32-Byte Burst (PCI Bus, 64-Bit)
T0
T1
T2
T3
T4
T5
T6
T7
T8
ADRS
D0
D1
D2
D3
CMD
BE0
BE1
BE2
BE3
clk
framen
ad
c_ben
irdyn
trdyn
stopn
irdyn



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