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OR3LP26B 데이터시트(PDF) 121 Page - Agere Systems

부품명 OR3LP26B
상세설명  Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
PDF  184 Pages
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OR3LP26B 데이터시트(HTML) 121 Page - Agere Systems

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Lucent Technologies Inc.
121
Data Sheet
ORCA OR3LP26B FPSC
March 2000
Embedded Master/Target PCI Interface
Lucent Technologies Inc.
PCI Bus Core Detailed Description Quad Port (continued)
Target Read Memory Burst, No Delayed Transaction
Figure 47 (PCI bus) and Figure 46 (FPGA bus) show the timing for a Target memory burst read of four Quadwords
handled as a nondelayed transaction. Figure 47 shows the timing on the PCI interface is similar to that of an I/O
read (Figure 40) except that stop is not asserted here to cause disconnect with data, but rather the operation is free
to continue since it is allowed to complete on the source (PCI) bus before it completes on the destination (FPGA)
bus.
5-8861(F).a
Figure 47. Target Read Memory Burst, No Delayed (PCI Bus, 32-Bit)
T0
T1
T2
T3
Tn0
Tn1
Tn2
Tn3
Tn4
Tn5
Tn6
X
ADRS
X
X
D0
D1
D2
D3
X
X
CMD
BE0
BE0
BE1
BE2
BE3
clk
framen
ad
c_ben
irdyn
devseln
trdyn
stopn



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