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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DP83848JSQ 데이터시트(PDF) 69 Page - Texas Instruments |
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DP83848JSQ 데이터시트(HTML) 69 Page - Texas Instruments |
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69 / 80 page  www.national.com 68 8.2.11 10 Mb/s MII Transmit Timing Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK. 8.2.12 10 Mb/s MII Receive Timing Note: RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Min- imum high and low times will not be violated. Parameter Description Notes Min Typ Max Units T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns TX_CLK TXD[3:0] TX_EN Valid Data T2.11.2 T2.11.3 T2.11.1 T2.11.1 Parameter Description Notes Min Typ Max Units T2.12.1 RX_CLK High/Low Time 160 200 240 ns T2.12.2 RX_CLK to RXD[3:0], RX_DV Delay 10 Mb/s MII mode 100 ns T2.12.3 RX_CLK rising edge delay from RXD[3:0], RX_DV Valid 10 Mb/s MII mode 100 ns RX_CLK RXD[3:0] RX_DV T2.12.2 T2.12.1 T2.12.1 T2.12.3 Valid Data |
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