DP83848JSQ datasheet(77/80 Pages) TI

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8.2.25 RMII Receive Timing

Note: Per the RMII Specification, output delays assume a 25pF load.

Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may

toggle synchronously at the end of the packet to indicate CRS deassertion.

Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of

receive data.

Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.

Note: CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of

CRS_DV.

Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the

Elasticity Buffer set to the default value (01).

Parameter

Description

Notes

Min

Typ

Max

Units

T2.25.1

X1 Clock Period

50 MHz Reference Clock

T2.25.2

RXD[1:0], CRS_DV, RX_DV,

and RX_ER output delay from

X1 rising

214

T2.25.3

CRS ON delay

From JK symbol on PMD Receive Pair to

initial assertion of CRS_DV

18.5

bits

T2.25.4

CRS OFF delay

From TR symbol on PMD Receive Pair to

initial deassertion of CRS_DV

bits

T2.25.5

RXD[1:0] and RX_ER latency

From symbol on Receive Pair. Elasticity

buffer set to default value (01)

bits

CRS_DV

RXD[1:0]

RX_ER

T2.25.2

T2.25.1

T2.25.2

PMD Input Pair

IDLE

Data

(J/K)

T2.25.3

T2.25.5

Data

(TR)

T2.25.4

RX_DV

T2.25.2

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