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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DP83848JSQ 데이터시트(PDF) 78 Page - Texas Instruments |
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DP83848JSQ 데이터시트(HTML) 78 Page - Texas Instruments |
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78 / 80 page  77 www.national.com 8.2.26 Isolation Timing 8.2.27 100 Mb/s X1 to TX_CLK Timing Note: X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. Clear bit 10 of BMCR (return to normal operation from Isolate mode) H/W or S/W Reset (with PHYAD = 00000) MODE ISOLATE NORMAL T2.26.2 T2.26.1 Parameter Description Notes Min Typ Max Units T2.26.1 From software clear of bit 10 in the BMCR register to the transi- tion from Isolate to Normal Mode 100 µs T2.26.2 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 500 µs X1 T2.27.1 TX_CLK Parameter Description Notes Min Typ Max Units T2.27.1 X1 to TX_CLK delay 100 Mb/s Normal mode 0 5 ns |
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