MPC8315CVRADDA datasheet(21/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

DDR and DDR2 SDRAM

This figure shows the DDR SDRAM input AC timing for the tolerated MDQS to MDQ skew (tDISKEW)

Figure 6. Timing Diagram for tDISKEW

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to

be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be

determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is

the absolute value of tCISKEW.

3. Memory controller ODT value of 150

 is recommended.

Table 19. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of (2.5V ± 200 mV)

Parameter

Symbol

Min

Max

Unit

Note

Controller Skew for MDQS—MDQ

266 MHz

200 MHz

tCISKEW

–750

–1250

750

1250

1, 2

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to

be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

Table 18. DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 V± 100 mV)

Parameter

Symbol

Min

Max

Unit

Note

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

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