| 전자부품 데이터시트 검색엔진 |
|
MPC8315CVRADDA 데이터시트(PDF) 54 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8315CVRADDA 데이터시트(HTML) 54 Page - Freescale Semiconductor, Inc |
|
54 / 106 page ![]() MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2 54 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) • The maximum average current requirement that also determines the common mode voltage range — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4V (0.4V/50 = 8mA) while the minimum common mode input level is 0.1V above XCOREVSS. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA (0-0.8V), such that each phase of the differential input has a single-ended swing from 0V to 800mV with the common mode voltage at 400mV. — If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 ohms to XCOREVSS DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. Figure 39. Receiver of SerDes Reference Clocks 15.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8315E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • Differential Mode — The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For external DC-coupled connection, as described in section 15.2.1, the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be Input Amp 50 50 SD_REF_CLK SD_REF_CLK |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |