MPC8315CVRADDA datasheet(56/106 Pages) FREESCALE

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 42. Single-Ended Reference Clock Input DC Requirements

15.2.3

Interfacing With Other Differential Signaling Levels

With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL (High-Speed

Current Steering Logic) compatible DC-coupled.

Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling) can be

used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400

mV) for DC-coupled connection.

LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock

driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to

AC-coupling.

NOTE

Figure 43–Figure 46 are for conceptual reference only. Due to the fact that

clock driver chip's internal structure, output impedance and termination

requirements are different between various clock driver chip manufacturers,

it’s very possible that the clock circuit reference designs provided by clock

driver chip vendor are different from what is shown below. They might also

vary from one vendor to the other. Therefore, Freescale Semiconductor can

neither provide the optimal clock driver reference circuits, nor guarantee the

correctness of the following clock driver connection reference circuits. The

system designer is recommended to contact the selected clock driver chip

vendor for the optimal reference circuits with the MPC8315E SerDes

reference clock receiver requirement provided in this document.

SD_REF_CLK

400 mV < SD_REF_CLK Input Amplitude < 800 mV

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