STM32F102X8 datasheet(66/80 Pages) STMICROELECTRONICS

66 / 80 page

Electrical characteristics

STM32F102x8, STM32F102xB

66/80

DocID15056 Rev 5

Equation 1: RAIN max formula:

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an

error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 45. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Power supply

2.4

3.6

fADC

ADC clock frequency

0.6

MHz

fS(1)

1. Guaranteed by design, not tested in production.

Sampling rate

0.05

0.85

Msps

fTRIG(1) External trigger frequency

fADC = 12 MHz

823

kHz

1/fADC

VAIN

Conversion voltage range(2)

2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA,

0 (VSSA or

VREF- tied to

ground)

VREF+

RAIN(1) External input impedance

See Equation 1

and Table 48

for details

κΩ

RADC(1) Sampling switch resistance

κΩ

CADC(1)

Internal sample and hold

capacitor

8pF

tCAL(1)

Calibration time

fADC = 12 MHz

5.9

µs

1/fADC

tlat(1)

Injection trigger conversion

latency

fADC = 12 MHz

0.214

µs

3(3)

3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 47.

1/fADC

tlatr(1)

Regular trigger conversion

latency

fADC = 12 MHz

0.143

µs

2(3)

1/fADC

tS(1)

Sampling time

fADC = 12 MHz

0.125

19.95

µs

1.5

239.5

1/fADC

tSTAB(1)

Power-up time

µs

tCONV(1)

Total conversion time

(including sampling time)

fADC = 12 MHz

1.2

µs

14 to 252 (tS for sampling +12.5

for successive approximation)

1/fADC

AIN

ADC

()

-------------------------------------------------------------

ADC

–

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