MPC8306SEC datasheet(30/70 Pages) FREESCALE

30 / 70 page

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

HDLC

The following figure provides the AC test load.

Figure 20. AC Test Load

Figure 21 and Figure 22 represent the AC timing from Table 29. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

The following figure shows the timing with external clock.

Figure 21. AC Timing (External Clock) Diagram

Outputs—External clock high impedance

tHEKHOX

Inputs—Internal clock input setup time

tHIIVKH

9—

Inputs—External clock input setup time

tHEIVKH

4—

Inputs—Internal clock input hold time

tHIIXKH

0—

Inputs—External clock input hold time

tHEIXKH

1—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs

internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

Table 29. HDLC AC Timing Specifications1 (continued)

Characteristic

Symbol2

Min

Max

Unit

Output

Z0 = 50 

OVDD/2

RL = 50 

Serial CLK (Input)

tHEIXKH

tHEIVKH

tHEKHOV

Input Signals:

(See Note)

Output Signals:

(See Note)

Note:

The clock edge is selectable.

tHEKHOX

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