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MPC8306SEC 데이터시트(PDF) 54 Page - Freescale Semiconductor, Inc |
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MPC8306SEC 데이터시트(HTML) 54 Page - Freescale Semiconductor, Inc |
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54 / 70 page ![]() MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1 54 Freescale Semiconductor Clocking 20 Clocking The following figure Figure 39 shows the internal distribution of clocks within the MPC8306S. Figure 38. MPC8306S Clock Subsystem Figure 39. MPC8306S Clock Subsystem The primary clock source for MPC8306S is SYS_CLK_IN. Figure 40. Core PLL System LBC LCLK[0:1] core_clk e300c3 core csb_clk to rest csb_clk Local Bus Clock Unit of the device lbc_clk QE PLL Memory Device /n to local bus Clock MEMC_MCK MEMC_MCK DDR ddr_clk DDR Memory Device PLL to DDR memory controller Clock /2 Divider Divider qe_clk MPC8306S CLK Gen QE_CLK_IN QE Block SYS_CLK_IN |
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