MPC8306SEC datasheet(2/70 Pages) FREESCALE

2 / 70 page

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

Overview

The MPC8306S incorporates the e300c3 (MPC603e-based) core built on Power Architecture®

technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and

on-chip memory management units (MMUs). The MPC8306S also includes two DMA engines and a

16-bit DDR2 memory controller.

A new communications complex based on QUICC Engine technology forms the heart of the networking

capability of the MPC8306S. The QUICC Engine block contains several peripheral controllers and a

32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified

communication controllers (UCCs). A block diagram of the MPC8306S is shown in the following figure.

Figure 1. MPC8306S Block Diagram

Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII

Ethernet, HDLC and TDM.

3 RMII/MII

2x TDM Ports

16-KB

D-Cache

16-KB

I-Cache

e300c3 Core with Power

2 x DUART

Interrupt

I2C

Timers

GPIO

DDR2

Controller

Baud Rate

Generators

Accelerators

Single 32-bit RISC CP Serial DMA

Serial Interface

QUICC Engine™ Block

Time Slot Assigner

16 KB Multi-User RAM

FPU

Management

SPI

RTC

2x HDLC

DMA

48 KB Instruction RAM

Engine

USB 2.0 HS

Host/Device/OTG

ULPI

Enhanced Local

Bus Controller

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