MPC8306SEC datasheet(13/70 Pages) FREESCALE

13 / 70 page

MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1

Freescale Semiconductor

DDR2 SDRAM

The following table provides the PLL lock times.

5.1

Reset Signals DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8306S reset signals mentioned

in Table 9.

6DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the

MPC8306S. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V.

6.1

DDR2 SDRAM DC Electrical Characteristics

The following table provides the recommended operating conditions for the DDR2 SDRAM component(s)

of the MPC8306S when GVDD(typ) = 1.8 V.

Table 10. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Note

PLL lock times

—

100

s—

Table 11. Reset Signals DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Note

Output high voltage

VOH

IOH = –6.0 mA

2.4

—

Output low voltage

VOL

IOL = 6.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Input high voltage

VIH

—2.0

OVDD +0.3

Input low voltage

VIL

—–0.3

0.8

—

Input current

IIN

0 V

 VIN  OVDD

—

±5

A—

Note:

1. This specification applies when operating from 3.3 V supply.

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Note

I/O supply voltage

GVDD

1.7

1.9

I/O reference voltage

MVREF

0.49

 GVDD

0.51

 GVDD

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

Input high voltage

VIH

MVREF+ 0.125

GVDD +0.3

—

Input low voltage

VIL

–0.3

MVREF – 0.125

—

Output leakage current

IOZ

–9.9

9.9

A4

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