AX2000 datasheet(31/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

2 - 17

Using the Weak Pull-Up and Pull-Down Circuits

Each Axcelerator I/O comes with a weak pull-up/down circuit (on the order of 10 k

Ω). These are weak

transistors with the gates tied on, so the on resistance of the transistor emulates a resistor. The weak

pull-up and pull-down is active only when the device is powered up, and they must be biased to be on.

When the rails are coming up, they are not biased fully, so they do not behave as resistors until the

voltage is at sufficient levels to bias the transistors. The key is they really are transistors; they are not

traces of poly silicon, which is another way to do an on-chip resistor (those take much more room). I/O

macros are provided for combinations of pull up/down for LVTTL, LVCMOS (2.5 V, 1.8 V, and 1.5 V)

standards. These macros can be instantiated if a keeper circuit for any input buffer is required.

Customizing the I/O

•

A five-bit programmable input delay element is associated with each I/O. The value of this delay is

set on a bank-wide basis (Table 2-14). It is optional for each input buffer within the bank (i.e. the

user can enable or disable the delay element for the I/O). When the input buffer drives a register

within the I/O, the delay element is activated by default to ensure a zero hold-time. The default

setting for this property can be set in Designer. When the input buffer does not drive a register, the

delay element is deactivated to provide higher performance. Again, this can be overridden by

changing the default setting for this property in Designer.

•

The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow

or fast.

•

The drive strength value for LVTTL output buffers can be programmed as well. There are four

different drive strength values – 8 mA, 12 mA, 16 mA, or 24 mA – that can be specified in

Designer.5

Table 2-14 • Bank-Wide Delay Values

Bits Setting

Delay (ns)

Bits Setting

Delay (ns)

00.54

2.01

10.65

2.13

20.71

2.19

30.83

2.3

0.9

2.38

51.01

2.49

61.08

2.55

71.19

2.67

81.27

2.75

91.39

2.87

1.45

2.93

1.56

3.04

1.64

3.12

1.75

3.23

1.81

3.29

1.93

3.41

Note:

Delay values are approximate and will vary with process, temperature, and voltage.

These values are minimum drive strengths.

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