| 전자부품 데이터시트 검색엔진 |
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AX2000 데이터시트(PDF) 96 Page - Microsemi Corporation |
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AX2000 데이터시트(HTML) 96 Page - Microsemi Corporation |
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96 / 262 page ![]() Detailed Specifications 2- 82 R e v i sio n 1 8 User Flow There are two methods of including a PLL in a design: • The recommended method of using a PLL is to create custom PLL blocks using Microsemi's macro generator, SmartGen, that can be instantiated in a design. • The alternative method is to instantiate one of the generic library primitives (PLL or PLLFB) into either a schematic or HDL netlist, using inverters for polarity control and tying all unused address and data bits to ground. Timing Model Note: tPCLK is the delay in the clock signal Figure 2-52 • PLL Model CLK CLK1 Lock CLK2 63 5 6 FB tPCLK* |
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