AX2000 datasheet(45/262 Pages) MICROSEMI

45 / 262 page

Axcelerator Family FPGAs

Re vi s i on 18

2 - 31

LVTTL Output Drive Strength = 2 (12 mA) / High Slew Rate

tDP

Input Buffer

1.68

1.92

2.26

tPY

Output Buffer

3.30

3.76

4.42

tENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

3.74

4.26

5.00

tENZH

Enable to Pad Delay through the Output Buffer—Z to

High

3.06

3.49

4.10

tENLZ

Enable to Pad Delay through the Output Buffer—Low

to Z

1.89

1.91

tENHZ

Enable to Pad Delay through the Output Buffer—High

to Z

2.29

2.30

2.31

tIOCLKQ

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

tIOCLKY

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

0.67

0.77

0.90

tSUD

Data Input Set-Up

0.23

0.27

0.31

tSUE

Enable Input Set-Up

0.26

0.30

0.35

tHD

Data Input Hold

0.00

tHE

Enable Input Hold

0.00

tCPWHL

Clock Pulse Width High to Low

0.39

tCPWLH

Clock Pulse Width Low to High

0.39

tWASYN

Asynchronous Pulse Width

0.37

tREASYN

Asynchronous Recovery Time

0.13

0.15

0.17

tHASYN

Asynchronous Removal Time

0.00

tCLR

Asynchronous Clear-to-Q

0.23

0.27

0.31

tPRESET

Asynchronous Preset-to-Q

0.23

0.27

0.31

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C (continued)

–2 Speed

–1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

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