AX2000 datasheet(19/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

Re vi s i on 18

2-5

Poutputs = PI/O * po * Fpo

Pmemory = P11 * Nblock * FRCLK + P12 * Nblock * FWCLK

PPLL = P13 * FCLK

Power Estimation Example

This example employs an AX1000 shift-register design with 1,080 R-cells, one C-cell, one reset input,

and one LVTTL 12 mA output, with high slew.

This design uses one HCLK at 100 MHz.

Cload = the output load (technology dependent)

VCCI = the output voltage (technology dependent)

= the number of outputs

Fpo

= the average output frequency

Nblock = the number of RAM/FIFO blocks (1 block = 4k)

FRCLK = the read-clock frequency of the memory

FWCLK = the write-clock frequency of the memory

FRefCLK = the clock frequency of the clock input of the PLL

FCLK

= the clock frequency of the first clock output of the PLL

ms =

1,080 (in a shift register - 100% of R-cells are toggling at each clock cycle)

100 MHz

1080

=> PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs = 79 mW

and Fs = 100 MHz

=> PR-cells = P7 * ms * Fs = 173 mW

mc =

1 (1 C-cell in this shift-register)

and Fs = 100 MHz

=> PC-cells = P8 * mc * Fs = 0.14 mW

Fpi ~ 0 MHz

and pi= 1 (1 reset input => this is why Fpi=0)

=> Pinputs = P9 * pi * Fpi = 0 mW

Fpo = 50 MHz

and po = 1

=> Poutputs = PI/O * po * Fpo= 27.10 mW

No RAM/FIFO in this shift-register

=> Pmemory = 0 mW

No PLL in this shift-register

=> PPLL = 0 mW

Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL = 276 mW

Pdc = 7.5mA * 1.5V = 11.25 mW

Ptotal = Pdc + Pac = 11.25 mW + 276mW = 290.30 mW

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