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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AX2000 데이터시트(PDF) 118 Page - Microsemi Corporation |
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AX2000 데이터시트(HTML) 118 Page - Microsemi Corporation |
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118 / 262 page  Detailed Specifications 2- 10 4 R ev isio n 1 8 Table 2-100 • Four FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Units Parameter Description Min. Max. Min. Max. Min. Max. FIFO Module Timing tWSU Write Setup 14.60 16.63 19.55 ns tWHD Write Hold 0.00 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 2.51 2.51 2.51 ns tWCKP Minimum WCLK Period 3.26 3.26 3.26 ns tRSU Read Setup 15.27 17.39 20.44 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 0.73 ns tRCKL RCLK Low 2.96 2.96 2.96 ns tRCKP Minimum RCLK period 3.69 3.69 3.69 ns tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 2.36 2.69 3.16 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 2.83 3.23 3.79 ns Note: Timing data for these four cascaded FIFO blocks uses a depth of 16,384. For all other combinations, use Microsemi’s timing software. |
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