CS494002 datasheet(70/100 Pages) CIRRUS

70 / 100 page

length is fixed to 8. We recommed SDRAM with a

CAS latency of 2 for optimal performance. The

refresh rate and the mode register of the SDRAM

must be set before Kickstart. Refer to Table 14,

“SDRAM Config Register,” on page 70 for details

on the SDRAM config register. The SDRAM is

initialized after Kickstart.

7.1 Configuring SRAM Timing Parameters

Since not all SRAM manufacturers conform to the

exact same timing specifications, it is necessary to

configure

the

DSP

match

the

timing

specifications of the particular SRAM that is used

in your design. This message must be sent before

Kickstarting the downloaded DSPC application

code.

SD_DATA15

SDRAM Data 15

SD_ADDR0

SDRAM Address 0

SD_ADDR1

SDRAM Address 1

SD_ADDR2

SDRAM Address 2

SD_ADDR3

SDRAM Address 3

SD_ADDR4

SDRAM Address 4

SD_ADDR5

SDRAM Address 5

SD_ADDR6

SDRAM Address 6

SD_ADDR7

SDRAM Address 7

SD_ADDR8

SDRAM Address 8

SD_ADDR9

SDRAM Address 9

SD_ADDR10

SDRAM Address

SD_DQM0

SDRAM Data

Mask Output0

SD_WE#

SDRAM Write

Enable

SD_CAS#

SDRAM Column

Address Strobe

SD_RAS#

SDRAM Row

Address Strobe

SD_CS#

SDRAM Chip

Select

SD_BA

SDRAM Bank

Select

SD_DQM1

SDRAM Data

SD_CLK_IN

SDRAM Clock

Input

SD_CLK_OUT

SDRAM Clock

Output

SD_CLK_EN

SDRAM Clock

Enable

Pin Name

Pin Description

144-Pin

Number

Table 12. SDRAM Interface Pins

Mnemonic

Hex

Message

SRAM_CONTROLLER_TIMING

0xaaa = 0www wwrr rrre (in binary)

w = SRAM_FLASH_WR_CYCLE vari-

able found in the SRAM Switching char-

acteristics table in Section 1.19.

r = SRAM_FLASH_RD_CYCLE variable

found in the SRAM Switching character-

istics table in Section 1.19.

e = SRAM Enable/Disable = 0/1.

Default, aaa = 0x000

0x8100000F

0x00000aaa

Table 13. SRAM Controller Timing

Mnemonic

Hex

Message

SDRAM_CONFIG

aaaa = Auto refresh setting.

Forexample fora 16

µS refresh period

and a DCLK of 86 Mhz the value pro-

grammed should be:

16X10-6 X 86X106 = 0x(1376) = 0x0560

bbb = Mode register setting. These bits

set the 12 least significant bits in the

mode register. The bits are to the follow-

ing by default:

bits(2..0) = 011 = Burst length 8.

bit3 = 0 = Sequential Burst Type.

bits(6..4) = 010 = CAS latency of 2.

bits(8..7) = 00 = Mode Register Set.

bit9 = 0 = Write Burst.

bit(12..10) = 000 = reserved

e = SDRAM Enable/Disable

=0001/0000.

Default, 0xaaaabbbe = 0x0560008c0

0x81000017

0xaaaabbbe

Table 14. SDRAM Config Register

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