CS494002 datasheet(82/100 Pages) CIRRUS

82 / 100 page

MCLK is the master clock and is firmware

configurable to be either an input or an output. If

MCLK is to be used as an output, the internal PLL

must be used. As an output MCLK can be

configured to provide a 128Fs, 256Fs, or 512Fs

clock, where Fs is the output sample rate.

SCLK0 is the bit clock used to clock data out on

AUDATA0,

AUDATA1,

AUDATA2

and

AUDATA3. LRCLK0 is the data framing clock

whose frequency is typically equal to the sampling

frequency

for

AUDATA0,

AUDATA1,

AUDATA2 and AUDATA3.

SCLK1 is the bit clock used to clock data out on

AUDATA4,

AUDATA5,

AUDATA6

and

AUDATA7. LRCLK1 is the data framing clock

whose frequency is typically equal to the sampling

frequency

for

AUDATA4,

AUDATA5,

AUDATA6 and AUDATA7.

LRCLK0, LRCLK1, SCLK0 and SCLK1 can be

configured as either inputs (Slave) or outputs

(Master). A valid MCLK is required for all output

modes. When LRCLK0, LRCLK1, SCLK0 and

SCLK1 are configured as outputs, they are derived

from MCLK. Whether MCLK is configured as an

input or an output, an internal divider from the

MCLK signal is used to produce LRCLK0,

LRCLK1, SCLK0 and SCLK1. The ratios shown

in Table 26 give the possible SCLK values for

different MCLK frequencies. (All values are

expressed in terms of the sampling frequency, Fs.)

Both the AUDAT0 and AUDAT4 Digital Audio

Output porst are configurable to provide output for

two, four, or six channels of PCM data.

AUDATA1,

AUDATA2,

AUDATA3,

AUDATA5, AUDATA6 and AUDATA7 are only

capable of outputting two channels of PCM data.

Typically AUDATA[0:7] are configured for

outputting either left justified or I2S formatted data.

In a standard 5.1 channel AVR, AUDATA0,

AUDATA1 and AUDATA2 are used to output the

six discrete channels (Left, Center, Right, Left

Surround, Right Surround, and Subwoofer).

AUDATA3

can

used

with

AUDATA0,

AUDATA1 and AUDATA2 to support 7.1 output.

Alternatively AUDATA3 and AUDATA7 can be

used for dual zone support. AUDATA3 and

AUDATA7 are multiplexed with the XMT958

output so only one can be used at any one time.

Please

refer

AN208,

AN209

and

their

corresponding appendices for information about

which output modes are supported, as this is

specific to each application code.

11.6.1 S/PDIF Outputs

Both AUDATA3 and AUDATA7 digital audio

output ports are unique, in that they can serve either

an additional output for I2S or Left Justified PCM

data OR as IEC60959 bi-phase mark encoded data

S/PDIF transmitters. When either of these ports are

configured as a S/PDIF transmitter, the MCLK

required for such functionality can be provided

from either the internally locked PLL or from an

SCLK0

Serial Bit Clock for

AUDATA 0-3

104

LRCLK0

Frame Clock for

AUDATA 0-3

108

AUDATA3,X

MT958A

Serial Data Out 3,

IEC60958 Trans-

mitter

106

AUDATA2

Serial Data Out 2

107

AUDATA1

Serial Data Out 1

109

AUDATA0

Serial Data Out 0

110

Pin Name

Pin Description

144-Pin

Number

100-Pin

Number

Table 25. Digital Audio Output Port (Continued)

MCLK

(Fs)

SCLK (Fs)

128

256

512

128

384

256

512

Table 26. MCLK/SCLK Master Mode Ratios

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