CS494002 datasheet(51/100 Pages) CIRRUS

51 / 100 page

6.2.1 Host Message (HOSTMSG) Register, A[1:0] = 00b

HOSTMSG7–0

Host data to and from the DSP. A read or write of this register operates handshake bits be-

tween the internal DSP and the external host. This register typically passes multibyte messages

carrying microcode, control, and configuration data (messages are written MSB first). HOST-

MSG is physically implemented as two independent registers for input and output (Read and

write).

6.2.2 Host Control (CONTROL) Register, A[1:0] = 01b

Reserved

Always write a 0 for future compatibility.

CMPRST

When set, initializes the CMPDATA compressed data input channel. Writing a one to this bit

holds the port in reset. Writing zero enables the port. This bit must be low for normal operation.

(Write only)

PCMRST

When set, initializes the PCMDATA linear PCM input channel. Writing a one to this bit holds the

port in reset. Writing zero enables the port. This bit must be low for normal operation. (Write

only)

MFC

When high, indicates that the PCMDATA input buffer is almost full. (Read only)

MFB

When high, indicates that the CMPDATA input buffer is almost full. (Read only)

HINBSY

Set when the host writes to HOSTMSG. Cleared when the DSP reads data from the HOSTMSG

DSP. (Read only)

HOUTRDY

Set when the DSP writes to the HOSTMSG register. Cleared when the host reads data from

the HOSTMSG register. The DSP reads this bit to determine if the last DSP output byte has

been read by the host. (Read only)

Reserved

Always write a 0 for future compatibility.

6.2.3 PCM Data Input (PCMDATA) Register, A[1:0] = 10b

PCMDATA7–0

The host writes PCM data to the DSP input buffer at this address. (Write only)

6.2.4 Compressed Data Input (CMPDATA) Register, A[1:0] = 11b

76543

210

HOSTMSG7

HOSTMSG6

HOSTMSG5

HOSTMSG4

HOSTMSG3

HOSTMSG2

HOSTMSG1

HOSTMSG0

76543

210

Reserved

CMPRST

PCMRST

MFC

MFB

HINBSY

HOUTRDY

Reserved

76543

210

PCMDATA7

PCMDATA6

PCMDATA5

PCMDATA4

PCMDATA3

PCMDATA2

PCMDATA1

PCMDATA0

76543

210

CMPDATA7

CMPDATA6

CMPDATA5

CMPDATA4

CMPDATA3

CMPDATA2

CMPDATA1

CMPDATA0

Table 6. Parallel Input/Output Registers for DSPAB

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