System performance considerations

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Figure 9. Five masters request SRAM access

The latency associated to DMA1 to win the bus matrix again and access SRAM1 (for

example) is equal to the execution time of all pending requests coming from the other

masters.

2.1.3

BusMatrix arbitration and DMA transfer delays worst case

The latency seen by the DMA master port on one transaction depends on the other masters’

transfer types and lengths.

For instance, if we consider previous DMA1 & CPU example (Figure 8) with concurrency to

access SRAM, latency on the DMA transfer varies depending on the CPU transaction

length.

If bus access is first granted to the CPU and the CPU is not performing a single data

load/store, the DMA wait time to gain access to SRAM can expand from one AHB cycle for

a single data load/store to N AHB cycles, where N is the number of data words in the CPU

transaction.

The CPU locks the AHB bus to keep ownership and reduces latency during multiple

load/store operations and interrupts entry. This enhances firmware responsiveness but it

can result in delays on the DMA transaction.

Delay on DMA1 SRAM access when in concurrency with CPU depends on the type of

transfer:

•

CPU transfer issued by interrupt (context save): 8 AHB cycles

•

–

Transfers of up to 14 registers from/to memory

a. Latency due to transfer issued by LDM/STM instructions can be reduced by configuring compiler to split

load/store multiple instructions into single load/store instructions.