System performance considerations

AN4031

24/36

DocID022648 Rev 1

Figure 13. Memory-to-peripheral transfer states

2.2.3

DMA request arbitration

As described in Section 1.1.2, the STM32F2/F4 DMA embeds an arbiter that manages the

eight DMA stream requests based on their priorities for each of the two AHB master ports

(memory and peripheral ports) and launches the peripheral/memory access sequences.

When more than one DMA request is active, DMA needs to arbiter internally between the

active requests and decide which request is to be served first.

The following figure shows two circular DMA requests triggered at the same time by DMA

stream “request 1” and by DMA stream “request 2” (requests 1 and 2 could be any DMA

peripheral request). At the next AHB clock cycle, the DMA arbiter checks on the active

pending requests and grants access to the “request 1” stream which has the highest priority.

The next arbitration cycle occurs during the last data cycle of the “request 1” stream. At that

time, “request 1” is masked and the arbiter sees only “request 2” as active, so access is

reserved to “request 2” this time, and so on.

Figure 14. DMA request arbitration