AN4031 datasheet(32/36 Pages) STMICROELECTRONICS

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Tips and warnings while programming the DMA controller

AN4031

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DocID022648 Rev 1

Tips and warnings while programming the DMA

controller

Software sequence to disable DMA

To switch off a peripheral connected to a DMA stream request, it is mandatory to:

•

switch off the DMA stream to which the peripheral is connected,

•

wait until the EN bit in DMA_SxCR register is reset (“0”).

Only then can the peripheral be safely disabled.

Note:

In both cases, a Transfer Complete Interrupt Flag (TCIF in DMA_LISR or DMA_HISR) is set

to indicate the end of transfer due to the stream disable.

DMA flag management before enabling a new transfer

Before enabling a new transfer, the user must ensure that the Transfer Complete Interrupt

Flag (TCIF) in DMA_LISR or DMA_HISR is cleared.

As a general recommendation, it is advised to clear all flags in the DMA_LIFCR and

DMA_HIFCR registers before starting a new transfer.

Software sequence to enable DMA

The following software sequence applies when enabling DMA:

•

Configure the suitable DMA stream.

•

Enable the DMA stream used (set the EN bit in the DMA_SxCR register).

•

Enable the peripheral used.

Note:

If the user enables the used peripheral before the corresponding DMA stream, a “FEIF”

(FIFO Error Interrupt Flag) may be set due to the fact the DMA is not ready to provide the

first required data to the peripheral (in case of memory-to-peripheral transfer).

Memory-to-memory transfer while NDTR=0

When configuring a DMA stream to perform a memory-to-memory transfer in normal mode,

once NDTR reaches 0, the Transfer Complete is set. At that time, if the user sets the enable

bit (EN bit in DMA_SxCR) of this stream, the memory-to-memory transfer is automatically

re-triggered again with the last NDTR value.

DMA peripheral burst with PINC/MINC=0

DMA Burst feature with peripheral address increment (PINC) or memory address increment

(MINC) disable allows to address internal or external (FSMC) peripherals supporting Burst

(embedding FIFOs). This mode ensures that this DMA stream cannot be interrupted by

other DMA streams during its transactions.

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