AN4031 datasheet(25/36 Pages) STMICROELECTRONICS

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AN4031

System performance considerations

General recommendations:

•

The high-speed/high-bandwidth peripherals must have the highest DMA priorities. This

ensures that the maximum data latency is respected for these peripherals and over-

/under-run conditions are avoided.

•

In case of equal bandwidth requirements, it is recommended to assign a higher priority

to the peripherals working in Slave mode (which have no control on the data transfer

speed) compared with the ones working in Master mode (which may control the data

flow).

•

As the two DMAs can work in parallel based on the bus matrix multi-layer structure,

high-speed peripherals’ requests can be balanced between the two DMAs when

possible.

2.3

AHB-to-APB bridge

STM32F2/F4 devices embed two AHB-to-APB bridges, APB1 and APB2, to which the

peripherals are connected.

2.3.1

Dual AHB-to-APB port

The STM32F2/F4 AHB-to-APB bridge is a dual-port architecture that allows access through

two different paths:

•

A direct path (not crossing the bus matrix) that can be generated from DMA1 to APB1

or from DMA2 to APB2; in this case, access is not penalized by the bus matrix arbiter.

•

A common path (through the bus matrix) that can be generated either from the CPU or

from DMA2, which needs the bus matrix arbitration to win the bus.

2.3.2

AHB-to-APB bridge arbitration

Due to DMA’s direct paths implementation on these products, an arbiter is implemented at

the AHB-to-APB bridge level to solve concurrent access requests.

The following figure illustrates a concurrent access request at an AHB-APB1 bridge

generated by the CPU (accessed through the bus matrix) and DMA1 (accessed through

direct path).

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