AN4031 datasheet(30/36 Pages) STMICROELECTRONICS

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How to predict DMA latencies

AN4031

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DocID022648 Rev 1

3.2.2

SPI full duplex DMA transfer

This example is applicable to products STM32F2xx, STM32F405, STM32F407,

STM32F415, STM32F417, STM32F42x and STM32F43x, and is based on the SPI1

peripheral.

Two DMA requests are configured:

•

DMA2_Stream2 for SPI1_RX: this stream is configured to be the highest priority in

order to serve in time the SPI1 received data, and transfer it from the SPI1_DR register

to the SRAM buffer.

•

DMA2_Stream3 for SPI1_TX: this stream transfers data from the SRAM buffer to the

SPI1_DR register.

The AHB frequency is equal to the APB2 frequency (84 MHz) and SPI1 is configured to

operate at the maximum speed (42 MHz). DMA2_Stream2 (SPI1_RX) is triggered before

DMA2_Stream3 (SPI1_TX), which is triggered two AHB cycles later.

With this configuration, the CPU is polling infinitely on the I2C1_DR register. Knowing that

the I2C1 peripheral is mapped on APB1 and that the SPI1 peripheral is mapped on APB2,

the system paths are the following:

•

Direct path for DMA2 to access APB2 (not through bus matrix),

•

CPU accesses APB1 through bus matrix.

The aim is to demonstrate that the DMA timings are not impacted by the CPU polling on

APB1. The following figure summarizes the DMA timing for Transmit and Receive modes,

as well as the time scheduling for each operation:

Figure 16. SPI full duplex DMA transfer time

AN4031 데이터시트(PDF) 30 Page - STMicroelectronics